A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the enhancement of the speed performance of integrated circuits. A common component of an integrated circuit is interconnect for coupling the various components of the integrated circuit. Referring to FIG. 1A, a first interconnect structure 102 and a second interconnect structure 104 are formed on a first insulating layer 106 of an integrated circuit fabricated on a semiconductor wafer 108. For example, when the semiconductor wafer 108 is comprised of silicon, the first insulating layer 106 is typically comprised of silicon dioxide, and the first and second interconnect structures 102 and 104 may be aluminum metal lines.
A second insulating layer 110 is deposited to surround the first and second interconnect structures 102 and 104 and to fill the gaps between the interconnect structures 102 and 104 by a conformal deposition process, as known to one of ordinary skill in the art of integrated circuit fabrication. For enhancing the speed performance of the integrated circuit, the second insulating layer 110 surrounding the interconnect structures 102 and 104 is a dielectric material designed to have low dielectric constant. A dielectric material with low dielectric constant results in lower capacitance between the interconnect structures 102 and 104. Such lower capacitance results in higher speed performance of the integrated circuit and also in lower power dissipation. In addition, such lower capacitance results in lower cross-talk between the interconnect structures 102 and 104. Lower cross-talk between interconnect structures 102 and 104 is especially advantageous when the interconnect structures 102 and 104 are disposed closer together as device density continually increases.
Referring to FIG. 1A, a capping layer 112 is deposited on the second insulating layer 110 for various integrated circuit fabrication process steps, as known to one of ordinary skill in the art of integrated circuit fabrication. For example, the capping layer 112 may be an antireflective layer comprised of siliconoxynitride (SiON) used during a photolithography process, as known to one of ordinary skill in the art of integrated circuit fabrication. Alternatively, the capping layer 112 may be a diffusion barrier layer comprised of silicon nitride (SiN) or siliconoxynitride (SiON), a passivation layer comprised of silicon dioxide (SiO.sub.2) or silicon nitride (SiN), an etch stop layer comprised of silicon nitride (SiN) or silicon carbide (SiC) films, or an CMP (Chemical Mechanical Polishing) stop layer comprised of silicon dioxide (SiO.sub.2) or silicon nitride (SiN), for example, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIG. 1B, the first interconnect structure 102 and the second interconnect structure 104 are formed in a damascene process. A damascene process is used when the interconnect structures 102 and 104 are comprised of material such as copper that do not etch as easily as aluminum, as known to one of ordinary skill in the art of integrated circuit fabrication. In that case, a diffusion barrier insulating material 107 is deposited on the semiconductor substrate (or on a previous interconnect layer in other integrated circuits). In addition, the insulating layer 110 having low dielectric constant is deposited on the diffusion barrier insulating material 107. The capping layer 112 is then deposited on the insulating layer 110.
Then openings are formed through the capping layer 112, the insulating layer 110, and the diffusion barrier insulating material 107 for formation of the interconnect structures 102 and 104. Such openings are filled with copper for formation of the interconnect structures 102 and 104. A first diffusion barrier layer 103 is typically formed between the first interconnect structure 102 and the insulating layer 110 for preventing diffusion of copper from the first interconnect structure 102 into the insulating layer 110. Similarly, a second diffusion barrier layer 105 is typically formed between the second interconnect structure 104 and the insulating layer 110 for preventing diffusion of copper from the second interconnect structure 104 into the insulating layer 110. Such process steps for formation of the damascene metal interconnect structures 102 and 104 are known to one of ordinary skill in the art of integrated circuit fabrication. (Elements having the same reference number in FIGS. 1A and 1B refer to elements having similar structure and function.)
In the structures of either FIG. 1A or FIG. 1B, examples of dielectric materials having low dielectric constant for the second insulating layer 110 surrounding the interconnect structures 102 and 104 are fluorinated silicon dioxide, porous versions of silicon dioxide, organic doped silica, inorganic dielectrics such as HSQ (hydrogcnsilsesquioxane) and MSQ (methylsilsesquioxane), and organic dielectrics such as polyarylether material, as known to one of ordinary skill in the art of integrated circuit fabrication.
Referring to FIGS. 1A and 1B, the capping layer 112 is formed on the second insulating layer 110 comprised of such a dielectric having a low dielectric constant. For formation of the capping layer 112, an oxygen containing reactant may be used. However, certain types of dielectrics having low dielectric constant are comprised of chemical bonds that are chemically reactive with the oxygen containing reactant, especially when oxygen plasma is used during deposition of the capping layer 112 in a plasma enhanced deposition process. For example, HSQ (hydrogensilsesquioxane) is comprised of SiO.sub.3 H, and MSQ (methylsilsesquioxane) is comprised of SiO.sub.3 CH.sub.3 formed into a ladder structure or cage structure, and polyarylether material is comprised of --C--O--C-- bonds, as known to one of ordinary skill in the art of integrated circuit fabrication.
Such chemical bonds within the dielectrics having low dielectric constant are chemically reactive with oxygen containing reactants. When the capping layer 112 is formed using an oxygen containing reactant, on the insulating layer 110 comprised of such dielectrics having low dielectric constant, the oxygen containing reactant may react with such chemically reactive bonds causing the increase of the dielectric constant of the insulating layer 110. For example, oxygen containing reactants may react with the dielectric material of the insulating layer 110 having Si--H (silicon to hydrogen) bonds and Si--CH.sub.3 (silicon to methyl) bonds to replace such bonds with Si--OH (silicon to hydroxide) bonds. The Si--OH (silicon to hydroxide) bonds may then adsorb water (H.sub.2 O) from the atmosphere resulting in an increase in the dielectric constant of the insulating layer 110. Although the capping layer 112 is desired for various integrated circuit fabrication processes, a low dielectric constant is also desired for the insulating layer 110.
Thus, a mechanism is desired for forming the capping layer 112 while preserving the low dielectric constant of the dielectric material comprising the insulating layer 110.